Graph-ESBMC-PLC: Formal Verification of Graphical PLCopen LD Programs
Graph-ESBMC-PLC enables formal verification of graphical IEC 61131-3 Ladder Diagram programs by introducing a DFS-based resolver that converts graphical LD connections into valid GOTO intermediate representation. Validation on three real-world programs shows full IR generation and successful verification of safety properties at k=2 within 70ms, with no regression on textual benchmarks.