The article proposes Symphony, a hybrid programmable and specialized architecture designed to address memory system inefficiencies in current high-performance architectures like GPUs. It focuses on orchestrating data throughout the memory hierarchy to reduce unnecessary data movement and distance.

  • Symphony utilizes specialized reconfigurable units for roofline floating-point computations alongside data orchestration features such as address generation, data filtering, and sparse metadata processing.
  • Computation resources are distributed throughout the on-chip memory hierarchy to support both programmable and specialized tasks.
  • The architecture aims to handle a mix of sparse and dense algorithms that domain-specific accelerators typically cannot manage.

Symphony matches non-programmable ASIC performance on sparse tensor algebra while providing 31x improved runtime and 44x improved energy over a comparably provisioned GPU.