OpenAI has released initial performance results for Jalapeño, its first custom inference chip, demonstrating significant gains in speed and power efficiency compared to existing commercial systems. The company states that the new architecture allows for higher throughput and lower latency simultaneously, addressing a common trade-off in current hardware.
Anthropic and HHMI Janelia Research Campus have opened a research preview of the Model Hardware Standard (MHS), a shared specification designed to enable AI agents to safely operate physical devices in labs and manufacturing facilities. The standard reduces hardware integration time from weeks or months to hours by providing a unified driver that translates between operating systems and diverse hardware interfaces.
OpenAI has released the first measured performance results for Jalapeño, its custom inference chip, alongside a detailed overview of its integrated "abundant intelligence" compute strategy. The company outlines how it combines data centers, chips, models, and software to improve efficiency and economics across its entire system.
Researchers present ShareMMU, an IOMMU design that allows multiple untrusted accelerators to securely reuse pre-translated addresses within a shared virtual address space. This approach mitigates side-channel risks associated with large Shared Translation Lookaside Buffers (TLBs) while maintaining high performance.
Researchers propose Onyx, a cost-efficient approach to disk-oblivious approximate nearest neighbor (ANN) search that balances bandwidth and access count by inverting the design of state-of-the-art ORAM-ANN systems.
Researchers from NVIDIA have introduced GPIR, a system that accelerates Private Information Retrieval (PIR) on GPUs by addressing the high server-side computation and memory traffic inherent in lattice-based protocols. The system employs a stage-aware hybrid execution model that dynamically switches between operation-level and stage-level kernels to maximize on-chip data reuse.
A new study presents a unified system-level characterization of secure multiparty computation (MPC) and fully homomorphic encryption (FHE) for privacy-preserving machine learning inference. The work evaluates two MPC variants—arithmetic/binary sharing conversion and function secret sharing—alongside FHE across multiple CNN and Transformer models.
Beatriz Yankelevich of MIT’s Engineering Quantum Systems Group used GPT‑5.6 Sol, integrated with Codex, to autonomously run and refine routine measurements on superconducting qubits. This integration allows the AI agent to operate laboratory software, analyze results, and decide on subsequent steps without constant human supervision.
Researchers have introduced Twill, a system that formulates software pipelining (SWP) and warp specialization (WS) as a joint optimization problem solvable by off-the-shelf constraint solvers. This approach automates the derivation of optimal execution schedules for iterative programs on GPU architectures.
At the 37th Hot Chips conference, OpenAI presented benchmark details for its custom inference chip, Jalapeño, claiming superior performance per watt compared to NVIDIA's GB200 and GB300 systems. The chip delivers 1.5–1.9× more work per watt at peak throughput and 1.7–3.6× lower end-to-end latency, with deployment into OpenAI's infrastructure scheduled by year-end.
Alibaba has announced plans to develop an artificial intelligence model containing between 5 trillion and 10 trillion parameters. Alongside this roadmap, the company also unveiled a new custom chip designed to support its infrastructure needs.
Huawei has paused its international expansion of artificial intelligence chips because domestic demand within China is exceeding the available supply. This strategic shift means that competitors AMD and Nvidia no longer face immediate pressure from Huawei's global market entry.
A proposal on Hugging Face discusses two interconnected problems in AI: the reliance on training separate large models and the ecosystem's dependence on general-purpose GPUs.
The llama.cpp project released build b11059, which introduces significant updates to the Metal backend for Apple Silicon hardware. The primary change is the addition of F16 input support to the Fast Walsh-Hadamard Transform (FWHT) kernel, allowing it to read F16 sources directly without requiring a converted copy.
The llama.cpp project has increased the hoisted row-id limit for the Vulkan mul_mat_id operation from 256 to 1024 experts. This change addresses performance bottlenecks in models with large expert counts, such as Qwen3.8-Flash-Next, which previously ran on a slower code path due to shared array size constraints.
The llama.cpp project released version b10997, which includes a change to the Mixture of Experts (MoE) ncols_opt tile heuristic to support the RDNA3.5 architecture.
The llama.cpp b10994 release includes a fix for the Metal backend that resolves NaN outputs in the `mul_mm_id` operation when activation values exceed the f16 range. This defect previously caused models like Mistral Small 4 to produce entirely NaN vocabularies during prefill steps of 32 tokens or more on Apple Silicon devices.
The author has built MOLT, a Windows-first runtime for thermally aware QLoRA fine-tuning on consumer NVIDIA GPUs, and benchmarked it against Unsloth using one million Qwen 1.5B training targets on an RTX 4060 Laptop GPU.
A user has developed a custom implementation that allows the DeepSeek V4.1 model to run on NVIDIA A100 GPUs with performance exceeding the official API.
A proposal on the Hugging Face forums outlines a common GPU execution and memory-management layer designed to decouple application code from specific hardware vendors like NVIDIA, AMD, and Intel. The goal is to allow users to specify a memory budget rather than manually configuring backend-specific flags, device maps, or offloading strategies.