NVIDIA has engineered NVIDIA Confidential Computing (CC) as a solution to address data privacy, sovereignty, and security concerns during AI model inference. The technology is designed to provide a secure environment for processing data while it is in use, specifically targeting the needs of agentic AI applications. This approach aims to enable organizations to adopt AI without compromising on security or performance.
NVIDIA introduces Confidential Computing for secure AI inference
Zero-Overhead Telemetry Detects Hidden ML Training
A study evaluates GPU workload classification using only zero-overhead NVML telemetry. The classifier achieves 98.2% accuracy in identifying training workloads and 43-87% accuracy against adversarially disguised, unexpected workloads across 9 GPU models.
ShareMMU enables secure address translation sharing among untrusted accelerators with low overhead
Researchers present ShareMMU, an IOMMU design that allows multiple untrusted accelerators to securely reuse pre-translated addresses within a shared virtual address space. This approach mitigates side-channel risks associated with large Shared Translation Lookaside Buffers (TLBs) while maintaining high performance.
Onyx achieves 1.7-9.9x lower cost and 2.3-12.3x lower latency for disk-oblivious ANN search
Researchers propose Onyx, a cost-efficient approach to disk-oblivious approximate nearest neighbor (ANN) search that balances bandwidth and access count by inverting the design of state-of-the-art ORAM-ANN systems.
Privatar enables scalable privacy-preserving multi-user VR via secure offloading
Researchers introduce Privatar, a framework that offloads avatar reconstruction from headsets to untrusted local devices while safeguarding against data interception. The system leverages domain-specific knowledge of avatar reconstruction to achieve provably private offloading with minimal performance cost.
NVIDIA releases GPIR for GPU-accelerated private information retrieval
Researchers from NVIDIA have introduced GPIR, a system that accelerates Private Information Retrieval (PIR) on GPUs by addressing the high server-side computation and memory traffic inherent in lattice-based protocols. The system employs a stage-aware hybrid execution model that dynamically switches between operation-level and stage-level kernels to maximize on-chip data reuse.