FPGN framework enables ultra-fast programmable gate-based neural acceleration with differentiable LUTs

Researchers propose FPGN, an end-to-end physically-aware framework that bridges the gap between LUT-native learning and latency-optimized FPGA implementation. The system addresses previous limitations by introducing a hardware-aligned differentiable formulation for training FPGA-native LUT neurons.

• FPGN utilizes a structured LUT-native topology with a streaming hardware architecture to improve routing locality and timing closure.
• A latency-driven compiler leverages high-fidelity analytical Quality of Results models to automate design space exploration and hardware generation.
• Experiments demonstrate up to 205x latency reduction compared to representative FPGA-based BNN accelerators.
• The framework achieves up to 30x higher LUT efficiency than prior differentiable LUT-native networks while maintaining competitive inference accuracy.

FPGN closes the gap between theoretical potential and high-performance hardware by providing an automated flow for systematic design space exploration.